State of the art formal verification methods do not yield coverage metrics which provide a quantitative measurement of how much of a register transfer level (RTL) design has been exercised during verification. Properties can be gauged for completeness to determine if all outputs of a design have been tested over all possible input conditions. However, there is no analogous metric to provide a statement of structural coverage to determine if all of the lines of a hardware description language (HDL) representation of an RTL design have been executed during operation. Such a metric would be directly comparable to simulation metrics to provide a statement of structural coverage.